The background description provided herein is for the purpose of generally presenting the context of the disclosure. Work of the inventors hereof, to the extent the work is described in this background section, as well as aspects of the description that does not otherwise qualify as prior art at the time of filing, are neither expressly nor impliedly admitted to be prior art against the present disclosure.
In communication systems, data can be sent from multiple data sources to multiple data destinations via a single gateway at a data interface, which usually limits the amount of data requests that the data interface is allowed to issue. For example, the single gateway receives a number of data requests from a number of data sources, and then forwards each of the data requests to a corresponding destination. In response to the number of data requests, the data interface subsequently receives a number of responses from the multiple destinations. To match each response with a corresponding data request, the order of the received responses is usually kept for each data source. For example, existing systems employ a buffer matrix at the data interface to store the data requests and their related attributes. Each row of the buffer matrix is a first-in-first-out (FIFO) buffer designated for data requests from the same data source. Thus, when a response intended for a data source is received, the response is matched with the corresponding data request that is output from the FIFO buffer corresponding to the respective data source. However, the buffer matrix structure often consumes significant area on a circuit when the data interface needs to handle data requests from a large number of data sources. In addition, the FIFO buffer designated for a particular source within each row of the buffer matrix is usually only partially filled, leading to inefficient utilization of the buffer space.